There is a continuous drive in the electronics industry to decrease the size of electronic devices in order to produce smaller packages and/or accommodate more electronic devices into existing packages. To this end, there is an increasing interest in using three dimensional (3D) stacked multi-chip semiconductor processes (e.g., through-silicon-vias (TSV), etc.) and package solutions to shrink the overall size of high-performance electronic systems. Chip stacking, or 3D integration, is the process of vertically assembling two or more integrated circuit (IC) chips so that the semiconductor chips that are placed in physical proximity to one another are also electrically connected to one another.
The effectiveness of a device in an integrated circuit chip is often affected when the size of the device is decreased. A common type of device in a chip is an on-chip transmission line comprising a coplanar waveguide (CPW). A traditional coplanar waveguide comprises a signal line flanked by two ground lines. All three lines, e.g., the signal line and the two ground lines, are formed in a common wiring level of a layered semiconductor structure and thus are coplanar in a substantially horizontal plane. The ever-present drive to reduce the size of integrated circuits has resulted in the shrinkage of the signal and ground lines in coplanar waveguides, which affects the signal-carrying effectiveness of a transmission lines comprising a coplanar waveguide.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.